View LT1054_82188.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1054/LT1054L Switched-Capacitor Voltage Converter with Regulator FEATURES
s s
DESCRIPTIO
s s
s s s s s
Available in Space Saving SO-8 Package Output Current: 100mA (LT1054) 125mA (LT1054L) Low Loss: 1.1V at 100mA Operating Range:3.5V to 15V (LT1054) 3.5V to 7V (LT1054L) Reference and Error Amplifier for Regulation External Shutdown External Oscillator Synchronization Can Be Paralleled Pin Compatible with the LTC(R)1044/LTC7660
The LT (R)1054 is a monolithic, bipolar, switched-capacitor voltage converter and regulator. The LT1054 provides higher output current than previously available converters with significantly lower voltage losses. An adaptive switch driver scheme optimizes efficiency over a wide range of output currents. Total voltage loss at 100mA output current is typically 1.1V. This holds true over the full supply voltage range of 3.5V to 15V. Quiescent current is typically 2.5mA. The LT1054 also provides regulation, a feature not previously available in switched-capacitor voltage converters. By adding an external resistive divider a regulated output can be obtained. This output will be regulated against changes in both input voltage and output current. The LT1054 can also be shut down by grounding the feedback pin. Supply current in shutdown is less than 100A. The internal oscillator of the LT1054 runs at a nominal frequency of 25kHz. The oscillator pin can be used to adjust the switching frequency or to externally synchronize the LT1054. The LT1054 is pin compatible with previous converters such the LTC1044/LTC7660.
APPLICATI
s s s s
S
Voltage Inverter Voltage Regulator Negative Voltage Doubler Positive Voltage Doubler
, LTC and LT are registered trademarks of Linear Technology Corporation.
BLOCK DIAGRAM
VREF 6 2.5V R
VIN 8
2
REFERENCE
DRIVE
VOLTAGE LOSS (V)
+
1 FEEDBACK/ SHUTDOWN
CAP + 2
+ -
OSC R 7 OSC Q Q CAP - 4 DRIVE DRIVE 3 GND *EXTERNAL CAPACITORS CIN*
1
+
COUT* 5 -VOUT DRIVE
LT1054 * BD
0
U
LT1054/LT1054L Voltage Loss
3.5V VIN 15V (LT1054) 3.5V VIN 7V (LT1054L) CIN = COUT = 100F INDICATES GUARANTEED TEST POINT LT1054 LT1054L TJ = 125C TJ = 25C TJ = -55C 0 25 50 75 100 OUTPUT CURRENT (mA) 125
1054 TA01*
W
UO
1
LT1054/LT1054L ABSOLUTE AXI U RATI GS
Supply Voltage (Note 2) LT1054 ................................................................ 16V LT1054L ................................................................ 7V Input Voltage Pin 1 ................................................. 0V VPIN1 V+ Pin 3 (S Package) ............................. 0V VPIN3 V+ Pin 7 ............................................. 0V VPIN7 VREF Pin 13 (S Package) ...................... 0V VPIN13 VREF Operating Junction Temperature Range LT1054C/LT1054LC ............................. 0C to 100C LT1054I ........................................... - 40C to 100C LT1054M ......................................... - 55C to 125C
PACKAGE/ORDER I FOR ATIO
TOP VIEW V+ 8 FB/SHDN 1 CAP + 2 7 OSC 6 VREF 5 VOUT
ORDER PART NUMBER LT1054CH LT1054MH
GND 3 CASE IS VOUT 4
CAP - H PACKAGE 8-LEAD TO-5 METAL CAN
TJMAX = 150C, JA = 150C, JC = 45C/W
TOP VIEW FB/SHDN 1 CAP + 2 GND 3 CAP - 4 J8 PACKAGE 8-LEAD CERAMIC DIP 8 7 6 5 V+ OSC VREF VOUT
O FO T R R EC EW O M DE ME SI D G ED S
ORDER PART NUMBER LT1054CJ8 LT1054CN8 LT1054IN8 LT1054MJ8
N8 PACKAGE 8-LEAD PLASTIC DIP
TJMAX = 150C, JA = 100C/ W (J8) TJMAX = 125C, JA = 130C/ W (N8)
2
U
U
W
WW
U
W
(Note 1)
Maximum Junction Temperature (Note 3) LT1054C/LT1054LC ........................................ 125C LT1054I ............................................................ 125C LT1054M ......................................................... 150C Storage Temperature Range H, J8, N8 and S8 Packages ................ -55C to 150C S Package ........................................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
(Note 6)
TOP VIEW FB/SHDN 1 CAP + 2 8 7 6 5 V+ OSC VREF VOUT
ORDER PART NUMBER LT1054CS8 LT1054LCS8 S8 PART MARKING 1054 1054L ORDER PART NUMBER LT1054CSW LT1054ISW
GND 3 CAP - 4
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 120C/W SEE REGULATION AND CAPACITOR SELECTION SECTIONS IN THE APPLICATIONS INFORMATION FOR IMPORTANT INFORMATION ON THE S8 DEVICE
TOP VIEW
NC 1 NC 2
16 NC 15 NC 14 V +
U U
W W
FB/SHDN 3 CAP + 4 GND 5 6
13 OSC
12 VREF
CAP -
11 VOUT 10 NC 9 NC
U
NC 7 NC 8
U
SW PACKAGE 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 150C/W
LT1054/LT1054L
ELECTRICAL CHARACTERISTICS
PARAMETER Supply Current CONDITIONS ILOAD = 0mA
(Note 7)
MIN VIN = 3.5V VIN = 15V LT1054L: VIN = 3.5V VIN = 7V LT1054:
q q q q q q q q q q q q q
TYP 2.5 3.0 2.5 3.0
Supply Voltage Range Voltage Loss (VIN - VOUT)
Output Resistance Oscillator Frequency Reference Voltage Regulated Voltage Line Regulation Load Regulation Maximum Switch Current Supply Current in Shutdown
LT1054 LT1054L CIN = COUT = 100F Tantalum (Note 4) IOUT = 10mA IOUT = 100mA IOUT = 125mA (LT1054L) IOUT = 10mA to 100mA (Note 5) LT1054: 3.5V VIN 15V LT1054L: 3.5V VIN 7V IREF = 60A, TJ = 25C VIN = 7V, TJ = 25C, RL = 500 (Note 6) LT1054: 7V VIN 12V, RL = 500 (Note 6) VIN = 7V, 100 RL 500 (Note 6) VPIN1 = 0V
3.5 3.5 0.35 1.10 1.35 10 25 25 2.50 - 5.00 5 10 300 100
MAX 4.0 5.0 4.0 5.0 15 7 0.55 1.60 1.75 15 35 35 2.65 2.75 - 5.20 25 50 200
UNITS mA mA mA mA V V V V V kHz kHz V V V mV mV mA A
15 15 2.35 2.25 - 4.70
q q q
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The absolute maximum supply voltage rating of 16V is for unregulated circuits using LT1054. For regulation mode circuits using LT1054 with VOUT 15V at Pin 5 (Pin 11 on S package), this rating may be increased to 20V. The absolute maximum supply voltage for LT1054L is 7V. Note 3: The devices are guaranteed by design to be functional up to the absolute maximum junction temperature. Note 4: For voltage loss tests, the device is connected as a voltage inverter, with pins 1, 6, and 7 (3, 12, and 13 S package) unconnected. The voltage losses may be higher in other configurations.
Note 5: Output resistance is defined as the slope of the curve, (VOUT vs IOUT), for output currents of 10mA to 100mA. This represents the linear portion of the curve. The incremental slope of the curve will be higher at currents < 10mA due to the characteristics of the switch transistors. Note 6: All regulation specifications are for a device connected as a positive-to-negative converter/regulator with R1 = 20k, R2 = 102.5k, C1 = 0.002F, (C1 = 0.05F S package) CIN = 10F tantalum, COUT = 100F tantalum. Note 7: The S8 package uses a different die than the H, J8, N8 and S packages. The S8 device will meet all the existing data sheet parameters. See Regulation and Capacitor Selection in the Applications Information section for differences in application requirements.
3
LT1054/LT1054L
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold
0.6 0.5
SHUTDOWN THRESHOLD (V)
SUPPLY CURRENT (mA)
VPIN1 0.4 0.3 0.2 0.1 0 - 50 - 25
3
FREQUENCY (kHz)
50 25 75 0 TEMPERATURE (C)
Supply Current in Shutdown
120
AVERAGE INPUT CURRENT (mA) 140 120
100
QUIESCENT CURRENT (A)
80 60 40 20 0
80 60 40 20 0 0 20 60 80 40 OUTPUT CURRENT (mA) 100
VOLTAGE LOSS (V)
VPIN1 = 0V
0
10 5 INPUT VOLTAGE (V)
Output Voltage Loss
INVERTER CONFIGURATION CIN = 10F TANTALUM COUT = 100F TANTALUM
2
VOLTAGE LOSS (V)
IOUT = 100mA
VOLTAGE LOSS (V)
1
0 1 10 OSCILLATOR FREQUENCY (kHz) 100
4
UW
100
LT1054 * TPC01
Supply Current
5 IL = 0 4
35
Oscillator Frequency
25 VIN = 3.5V
VIN = 15V
2
1
0
125
0
10 5 INPUT VOLTAGE (V)
15
LT1054 * TPC02
15 -70 -50 -25 0 25 50 75 TEMPERATURE (C)
100 125
LT1054 * TPC03
Average Input Current
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
Output Voltage Loss
IOUT = 100mA
100
IOUT = 50mA
IOUT = 10mA INVERTER CONFIGURATION COUT = 100F TANTALUM fOSC = 25kHz 0 10 20 30 40 50 60 70 80 90 100 INPUT CAPACITANCE (F)
LT1054 * TPC06
15
LT1054 * TPC04
LT1050 * TPC05
Output Voltage Loss
INVERTER CONFIGURATION CIN = 100F TANTALUM COUT = 100F TANTALUM
2
IOUT = 100mA 1 IOUT = 50mA IOUT = 10mA 0 1 10 OSCILLATOR FREQUENCY (kHz) 100
IOUT = 50mA IOUT = 10mA
LT1054 * TPC07
LT1054 * TPC08
LT1054/LT1054L
TYPICAL PERFOR A CE CHARACTERISTICS
Regulated Output Voltage
-4.7 100
-4.9
REFERENCE VOLTAGE CHANGE (mV)
-4.8
OUTPUT VOLTAGE (V)
-5.0 -5.1 -11.6 -11.8 -12.0 -12.2 -12.4 -12.6 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
PIN FUNCTIONS
FB/SHDN (Pin 1): Feedback/Shutdown Pin. This pin has two functions. Pulling Pin 1 below the shutdown threshold ( 0.45V) puts the device into shutdown. In shutdown the reference/regulator is turned off and switching stops. The switches are set such that both CIN and COUT are discharged through the output load. Quiescent current in shutdown drops to approximately 100A (see Typical Performance Characteristics). Any open-collector gate can be used to put the LT1054 into shutdown. For normal (unregulated) operation the device will start back up when the external gate is shut off. In LT1054 circuits that use the regulation feature, the external resistor divider can provide enough pull-down to keep the device in shutdown until the output capacitor (COUT) has fully discharged. For most applications where the LT1054 would be run intermittently, this does not present a problem because the discharge time of the output capacitor will be short compared to the offtime of the device. In applications where the device has to start up before the output capacitor (COUT) has fully discharged, a restart pulse must be applied to Pin 1 of the LT1054. Using the circuit of Figure 5, the restart signal can be either a pulse (tp > 100s) or a logic high. Diode coupling the restart signal into Pin 1 will allow the output voltage to come up and regulate without overshoot. The resistor divider R3/R4 in Figure 5 should be chosen to provide a signal level at pin 1 of 0.7V to 1.1V. Pin 1 is also the inverting input of the LT1054's error amplifier and as such can be used to obtain a regulated output voltage. CAP +/CAP - (Pin 2/Pin 4): Pin 2, the positive side of the input capacitor (CIN), is alternately driven between V + and ground. When driven to V +, Pin 2 sources current from V +. When driven to ground Pin 2 sinks current to ground. Pin 4, the negative side of the input capacitor, is driven alternately between ground the VOUT. When driven to ground, Pin 4 sinks current to ground. When driven to VOUT Pin 4 sources current from COUT. In all cases current flow in the switches is unidirectional as should be expected using bipolar switches. VOUT (Pin 5): In addition to being the output pin this pin is also tied to the substrate of the device. Special care must be taken in LT1054 circuits to avoid pulling this pin positive with respect to any of the other pins. Pulling Pin 5 positive with respect to Pin 3 (GND) will forward bias the substrate diode which will prevent the device from starting. This condition can occur when the output load driven by the LT1054 is referred to its positive supply (or to some other positive voltage). Note that most op amps present just such a load since their supply currents flow from their V + terminals to their V - terminals. To prevent start-up problems with this type of load an external transistor must be added as shown in Figure 1. This will prevent VOUT (Pin 5)
UW
Reference Voltage Temperature Coefficient
80 60 40 20 0 -20 -40 -60 -80 50 25 0 75 TEMPERATURE (C) 100 125 VREF AT 0 = 2.500V
-100 -50 -25
LT1054 * TPC09
LT1054 * TPC10
U
U
U
5
LT1054/LT1054L
PIN FUNCTIONS
from being pulled above the ground pin (Pin 3) during start-up. Any small, general purpose transistor such as 2N2222 or 2N2219 can be used. RX should be chosen to provide enough base drive to the external transistor so that it is saturated under nominal output voltage and maximum output current conditions. In some cases an N-channel enhancement mode MOSFET can be used in place of the transistor.
RX (|VOUT|) IOUT
V+
FB/SHDN
V+ RX
+
CIN
OSC CAP + LT1054 GND VREF CAP - VOUT
Figure 1
Figure 2
V + (Pin 8): Input Supply. The LT1054 alternately charges CIN to the input voltage when CIN is switched in parallel with the input supply and then transfers charge to COUT when CIN is switched in parallel with COUT. Switching occurs at
6
+
VREF (Pin 6): Reference Output. This pin provides a 2.5V reference point for use in LT1054-based regulator circuits. The temperature coefficient of the reference voltage has been adjusted so that the temperature coefficient of the regulated output voltage is close to zero. This requires the reference output to have a positive temperature coefficient as can be seen in the typical performance curves. This nonzero drift is necessary to offset a drift term inherent in the internal reference divider and comparator network tied to the feedback pin. The overall result of these drift terms is a regulated output which has a slight positive temperature coefficient at output voltages below 5V and a slight negative TC at output voltages above 5V. Reference output current should be limited, for regulator feedback networks, to approximately 60A. The reference pin will draw 100A when shorted to ground and will not affect the internal reference/regulator, so that this pin can also be used as a pull-up for LT1054 circuits that require synchronization.
+
U
U
U
OSC (Pin 7): Oscillator Pin. This pin can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock. Internally Pin 7 is connected to the oscillator timing capacitor (Ct 150pF) which is alternately charged and discharged by current sources of 7A so that the duty cycle is 50%. The LT1054 oscillator is designed to run in the frequency band where switching losses are minimized. However the frequency can be raised, lowered, or synchronized to an external system clock if necessary. The frequency can be lowered by adding an external capacitor (C1, Figure 2) from Pin 7 to ground. This will increase the charge and discharge times which lowers the oscillator frequency. The frequency can be increased by adding an external capacitor (C2, Figure 2, in the range of 5pF to 20pF) from Pin 2 to Pin 7. This capacitor will couple charge into CT at the switch transitions, which will shorten the charge and discharge time, raising the oscillator frequency. Synchronization can be accomplished by adding an external resistive pull-up from Pin 7 to the reference pin (Pin 6). A 20k pull-up is recommended. An open collector gate or an NPN transistor can then be used to drive the oscillator pin at the external clock frequency as shown in Figure 2. Pulling up Pin 7 to an external voltage is not recommended. For circuits that require both frequency synchronization and regulation, an external reference can be used as the reference point for the top of the R1/R2 divider allowing Pin 6 to be used as a pull-up point for Pin 7.
IL LOAD
+ -
IQ
IOUT
LT1054 * F01
COUT
FB/SHDN V +
VIN
C2
+
CIN
OSC CAP LT1054 GND VREF CAP
-
+
C1
VOUT COUT
LT1054 * F02
LT1054/LT1054L
PIN FUNCTIONS
the oscillator frequency. During the time that CIN is charging, the peak supply current will be approximately equal to 2.2 times the output current. During the time that CIN is delivering charge to COUT the supply current drops to approximately 0.2 times the output current. An input supply bypass capacitor will supply part of the peak input current drawn by the LT1054 and average out the current drawn from the supply. A minimum input supply bypass capacitor of 2F, preferably tantalum or some other low ESR type is recommended. A larger capacitor may be desirable in some cases, for example, when the actual input supply is connected to the LT1054 through long leads, or when the pulse current drawn by the LT1054 might affect other circuitry through supply coupling.
APPLICATIONS INFORMATION
Theory of Operation To understand the theory of operation of the LT1054, a review of a basic switched-capacitor building block is helpful. In Figure 3 when the switch is in the left position, capacitor C1 will charge to voltage V1. The total charge on C1 will be q1 = C1V1. The switch then moves to the right, discharging C1 to voltage V2. After this discharge time the charge on C1 is q2 = C1V2. Note that charge has been transferred from the source V1 to the output V2. The amount of charge transferred is: q = q1 - q2 = C1(V1 - V2) If the switch is cycled f times per second, the charge transfer per unit time (i.e., current) is: I = (f)(q) = (f)[C1(V1 - V2)] To obtain an equivalent resistance for the switched-capacitor network we can rewrite this equation in terms of voltage and impedance equivalence:
I = V1 - V2 = V1 - V2 (1/fC1) REQUIV
REQUIV V1 REQUIV = 1 fC1 C2 RL
LT1054 * F04
A new variable REQUIV is defined such that REQUIV = 1/fC1. Thus the equivalent circuit for the switched-capacitor network is as shown in Figure 4. The LT1054 has the same switching action as the basic switched-capacitor building block. Even though this simplification doesn't include finite switch on-resistance and output voltage ripple, it provides an intuitive feel for how the device works. These simplified circuits explain voltage loss as a function of frequency (see Typical Performance Characteristics). As frequency is decreased, the output impedance will eventu-
U
W
U
U
U
U
U
V1 f C1 C2 RL
V2
LT1054 * F03
Figure 3. Switched-Capacitor Building Block
V2
Figure 4. Switched-Capacitor Equivalent Circuit
ally be dominated by the 1/fC1 term and voltage losses will rise. Note that losses also rise as frequency increases. This is caused by internal switching losses which occur due to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied by the switching frequency, becomes a current loss. At high frequency this loss becomes significant and voltage losses again rise. The oscillator of the LT1054 is designed to run in the frequency band where voltage losses are at a minimum. Regulation The error amplifier of the LT1054 servos the drive to the PNP switch to control the voltage across the input capacitor (CIN) which in turn will determine the output voltage. Using the reference and error amplifier of the LT1054, an external resistive divider is all that is needed to set the regulated output voltage. Figure 5 shows the basic regulator configuration and the formula for calculating the appropriate resistor values. R1 should be chosen to be
7
LT1054/LT1054L
APPLICATIONS INFORMATION
R3 FB/SHDN V R4 CIN 10F TANTALUM
+
+
OSC CAP + LT1054 GND VREF CAP - VOUT
FOR EXAMPLE: TO GET VOUT = -5V REFERRED TO THE GROUND PIN OF THE LT1054, CHOOSE R1 = 20k, THEN R2 = 20k + 1 = 102.6k* 2.5V - 40mV 2 *CHOOSE THE CLOSEST 1% VALUE
)
|-5V|
)
Figure 5
20k or greater because the reference output current is limited to 100A. R2 should be chosen to be in the range of 100k to 300k. For optimum results the ratio of CIN/COUT is recommended to be 1/10. C1, required for good load regulation at light load currents, should be 0.002F for all output voltages. A new die layout was required to fit into the physical dimensions of the S8 package. Although the new die of the LT1054CS8 will meet all the specifications of the existing LT1054 data sheet, subtle differences in the layout of the new die require consideration in some application circuits. In regulating mode circuits using the 1054CS8 the nominal values of the capacitors, CIN and COUT, must be approximately equal for proper operation at elevated junction temperatures. This is different from the earlier part. Mismatches within normal production tolerances for the capacitors are acceptable. Making the nominal capacitor values equal will ensure proper operation at elevated junction temperatures at the cost of a small degradation in the transient response of regulator circuits. For unregulated circuits the values of CIN and COUT are normally equal for all packages. For S8 applications assistance in unusual applications circuits, please consult the factory. It can be seen from the circuit block diagram that the maximum regulated output voltage is limited by the supply
8
+
|VOUT| |VOUT| R2 = +1 +1 1.21V VREF R1 - 40mV 2 WHERE VREF = 2.5V NOMINAL
)
RESTART SHUTDOWN
)) )
VOUT COUT 100F TANTALUM
LT1054 * F05
+
VIN
U
W
U
U
2.2F
R1 R2 C1
voltage. For the basic configuration, |VOUT| referred to the ground pin of the LT1054 must be less than the total of the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due to the switches can be found in Typical Performance Characteristics. Other configurations such as the negative doubler can provide higher output voltages at reduced output currents (see Typical Applications). Capacitor Selection For unregulated circuits the nominal values of CIN and COUT should be equal. For regulated circuits see the section on Regulation. While the exact values of CIN and COUT are noncritical, good quality, low ESR capacitors such as solid tantalum are necessary to minimize voltage losses at high currents. For CIN the effect of the ESR of the capacitor will be multiplied by four due to the fact that switch currents are approximately two times higher than output current and losses will occur on both the charge and discharge cycle. This means that using a capacitor with 1 of ESR for CIN will have the same effect as increasing the output impedance of the LT1054 by 4. This represents a significant increase in the voltage losses. For COUT the affect of ESR is less dramatic. COUT is alternately charged and discharged at a current approximately equal to the output current and the ESR of the capacitor will cause a step function to occur in the output ripple at the switch transitions. This step function will degrade the output regulation for changes in output load current and should be avoided. Realizing that large value tantalum capacitors can be expensive, a technique that can be used is to parallel a smaller tantalum capacitor with a large aluminum electrolytic capacitor to gain both low ESR and reasonable cost. Where physical size is a concern some of the newer chip type surface mount tantalum capacitors can be used. These capacitors are normally rated at working voltages in the 10V to 20V range and exhibit very low ESR (in the range of 0.1). Output Ripple The peak-to-peak output ripple is determined by the value of the output capacitor and the output current. Peak-topeak output ripple may be approximated by the formula:
dV =
IOUT 2fCOUT
LT1054/LT1054L
APPLICATIONS INFORMATION
where dV = peak-to-peak ripple and f = oscillator frequency. For output capacitors with significant ESR a second term must be added to account for the voltage step at the switch transitions. This step is approximately equal to: (2IOUT)(ESR of COUT) Power Dissipation The power dissipation of any LT1054 circuit must be limited such that the junction temperature of the device does not exceed the maximum junction temperature ratings. The total power dissipation must be calculated from two components, the power loss due to voltage drops in the switches and the power loss due to drive current losses. The total power dissipated by the LT1054 can be calculated from: P (VIN - |VOUT|)(IOUT) + (VIN)(IOUT)(0.2) where both VIN and VOUT are referred to the ground pin (Pin 3) of the LT1054. For LT1054 regulator circuits, the power dissipation will be equivalent to that of a linear regulator. Due to the limited power handling capability of the LT1054 packages, the user will have to limit output current requirements or take steps to dissipate some power external to the LT1054 for large input/output differentials. This can be accomplished by placing a resistor in series with CIN as shown in Figure 6. A portion of the input voltage will then be dropped across this resistor without affecting the output regulation. Because switch current is approximately 2.2 times the output current and the resistor will cause a voltage drop when CIN is both charging and discharging, the resistor should be chosen as:
VIN FB/SHDN V + RX
+
CIN
OSC CAP + LT1054 GND VREF CAP - VOUT
R1 R2 C1
VOUT COUT
LT1054 * F06
Figure 6
U
W
+
U
U
RX = VX/(4.4 IOUT) where VX VIN - [(LT1054 Voltage Loss)(1.3) + |VOUT|] and IOUT = maximum required output current. The factor of 1.3 will allow some operating margin for the LT1054. For example: assume a 12V to - 5V converter at 100mA output current. First calculate the power dissipation without an external resistor: P = (12V - |-5V|)(100mA) + (12V)(100mA)(0.2) P = 700mW + 240mW = 940mW At JA of 130C/W for a commercial plastic device this would cause a junction temperature rise of 122C so that the device would exceed the maximum junction temperature at an ambient temperature of 25C. Now calculate the power dissipation with an external resistor (RX). First find how much voltage can be dropped across RX. The maximum voltage loss of the LT1054 in the standard regulator configuration at 100mA output current is 1.6V, so VX = 12V - [(1.6V)(1.3) + |-5V|] = 4.9V and RX = 4.9V/(4.4)(100mA) = 11 This resistor will reduce the power dissipated by the LT1054 by (4.9V)(100mA) = 490mW. The total power dissipated by the LT1054 would then be (940mW - 490mW) = 450mW. The junction temperature rise would now be only 58C. Although commercial devices are guaranteed to be functional up to a junction temperature of 125C, the specifications are only guaranteed up to a junction temperature of 100C, so ideally you should limit the junction temperature to 100C. For the above example this would mean limiting the ambient temperature to 42C. Other steps can be taken to allow higher ambient temperatures. The thermal resistance numbers for the LT1054 packages represent worst case numbers with no heat sinking and still air. Small clip-on type heat sinks can be used to lower the thermal resistance of the LT1054 package. In some systems there may be some available airflow which will help to lower the thermal resistance. Wide PC board traces from the LT1054 leads can also help to remove heat from the device. This is especially true for plastic packages.
9
LT1054/LT1054L
TYPICAL APPLICATIONS N
Basic Voltage Inverter
FB/SHDN V +
+
100F
+
-VOUT 100F
LT1054 * TAO2
CAP -
VOUT
10F
OSC CAP + LT1054 GND VREF CAP - VOUT
REFER TO FIGURE 5
Negative Voltage Doubler Positive Doubler
FB/SHDN V + OSC CAP LT1054 GND VREF CAP
- +
+
VOUT
1N4001 VOUT 50mA
VIN 1N4001 3.5V TO 15V
+
100F
-
QX* 100F RX*
+ -
VIN 2F
+
100F
+
10F FB/SHDN V + OSC CAP + LT1054 GND VREF CAP - VOUT
VOUT
+
VIN = 3.5V TO 15V VOUT 2VIN - (VL + 2VDIODE) VL = LT1054 VOLTAGE LOSS
VIN VIN = -3.5V TO -15V VOUT = 2VIN + (LT1054 VOLTAGE LOSS) + (QX SATURATION VOLTAGE) LT1054 * TAO4 *SEE FIGURE 3
100mA Regulating Negative Doubler
VIN 3.5 TO 15V
+
2.2F
FB/SHDN V +
FB/SHDN V + VOUT SET R1 40k 0.002F
HP5082-2810 20k PIN 2 LT1054 #1
+
10F 10F 1N4002
+
OSC CAP + LT1054 #1 GND VREF CAP - VOUT 10F
+
10F 10F 1N4002
+
OSC CAP + LT1054 #2 GND VREF CAP - VOUT
1N4002
100F
VIN = 3.5 TO 15V VOUT MAX -2VIN + [1054 VOLTAGE LOSS + 2(VDIODE)]
-VOUT IOUT 100mA MAX
LT1054 * TAO6
|VOUT| |VOUT| R2 = +1 = + 1 , REFER TO FIGURE 5 1.21V R1 VREF - 40mV 2
)
)) )
10
+
1N4002
R2 500k
1N4002
10F
+
|VOUT| |VOUT| R2 = +1 = +1 , 1.21V R1 VREF - 40mV 2
)
)) )
VOUT 100F
LT1054 * TA03
+
OSC CAP + LT1054 GND VREF
+
+
U
Basic Voltage Inverter/Regulator +
VIN 2F
VIN FB/SHDN V +
2F
R1 R2 0.002F
+
2F
+
LT1054 * TAO5
+
LT1054/LT1054L
TYPICAL APPLICATIONS N
Bipolar Supply Doubler
VIN 3.5V TO 15V
+VOUT
= 1N4001
5V to 12V Converter
VIN = 5V
+
5F
+
FB/SHDN V
+
VOUT 12V IOUT = 25mA
1N914
1N914
+
100F
+
10F FB/SHDN V + OSC CAP + LT1054 #2 GND VREF CAP - VOUT TO PIN 4 LT1054 #1 20k VOUT -12V IOUT = 25mA
LT1054 * TAO8
+
10F
OSC CAP LT1054 #1 GND VREF CAP - VOUT 100F 1k 2N2219
+
10F 5F
Strain Gauge Bridge Signal Conditioner
10k INPUT TTL OR CMOS LOW FOR ON 10k 2N2907 5V
+
40 10k ZERO TRIM 10F
1
A1 1/2 LT1013
301k 3 100k 350 1F 10k 5
200k FB/SHDN V + 5V 3k 2N2222
+
10F
OSC CAP + LT1054 GND VREF CAP - VOUT
+ 100F
TANTALUM
A = 125 FOR 0V TO 3V OUT FROM FULL-SCALE BRIDGE OUTPUT OF 24mV
+
-
-
0.022F
8
2
100k
5k
5k GAIN TRIM 6 1M 7 A2 1/2 LT1013 4
+
+
+
VIN = 3.5V TO 15V +VOUT 2VIN - (VL + 2VDIODE) -VOUT -2VIN + (VL + 2VDIODE) VL = LT1054 VOLTAGE LOSS
100F
-
+
+
+
U
+ -
+
100F
+
10F FB/SHDN V + OSC CAP + LT1054 GND VREF CAP - 10F -VOUT VOUT
+
10F
100F
+
+
LT1054 * TAO7
100F
LT1054 * TAO9
11
LT1054/LT1054L
TYPICAL APPLICATIONS N
VIN 3.5V TO 5.5V
20k
1N914
1N914 FB/SHDN 1N914
+
+
10F
R2 125k 2N2219
100F
3k
VOUT = 5V
VIN = 3.5V TO 5.5V VOUT = 5V IOUT(MAX) = 50mA 1N5817
1N914
LT1054 * TA10
Regulating 200mA, 12V to - 5V Converter
5F 12V
FB/SHDN V + OSC CAP + LT1054 #1 GND VREF CAP - VOUT R1 39.2k 10F R2 200k 200F 0.002F
FB/SHDN V +
HP5082-2810
10 1/2W
+
10F
10 1/2W
OSC CAP + LT1054 #2 GND VREF CAP - VOUT
20k
+
REFER TO FIGURE 5
Digitally Programmable Negative Supply
15V
+
5F 20k LT1004-2.5 2.5V 20k 14 16
FB/SHDN V +
+
10F
OSC CAP + LT1054 GND VREF CAP - VOUT
VOUT = -VIN (PROGRAMMED) 100F
12
+
|VOUT| |VOUT| R2 = +1 = +1 , 1.21V R1 VREF - 40mV 2
)
)) )
LT1054 * TA11
VOUT = -5V IOUT = 0mA to 200mA
11
AD558
DIGITAL INPUT
13
12
LT1054 * TA12
+
CAP -
VOUT
0.002F
+
+
-
+
+
U
3.5V to 5V Regulator
1
8 7 LTC1044 6 5
+
V+ R1 20k
2 3 4
+
5F R2 125k
1F
OSC CAP LT1054 GND VREF
1F
LT1054/LT1054L
PACKAGE DESCRIPTION
0.040 (1.016) MAX
SEATING PLANE 0.010 - 0.045* (0.254 - 1.143) 0.016 - 0.021** (0.406 - 0.533)
45TYP 0.028 - 0.034 (0.711 - 0.864)
0.110 - 0.160 (2.794 - 4.064) INSULATING STANDOFF
CORNER LEADS OPTION (4 PLCS)
0.045 - 0.068 (1.143 - 1.727) FULL LEAD OPTION 0.300 BSC (0.762 BSC)
0.008 - 0.018 (0.203 - 0.457)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS
U
Dimensions in inches (millimeters) unless otherwise noted. H Package 8-Lead TO-5 Metal Can (0.200 PCD)
(LTC DWG # 05-08-1320)
0.335 - 0.370 (8.509 - 9.398) DIA 0.305 - 0.335 (7.747 - 8.509) 0.050 (1.270) MAX GAUGE PLANE 0.165 - 0.185 (4.191 - 4.699) REFERENCE PLANE 0.500 - 0.750 (12.700 - 19.050)
0.027 - 0.045 (0.686 - 1.143) PIN 1
0.200 (5.080) TYP
*LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND 0.045" BELOW THE REFERENCE PLANE 0.016 - 0.024 **FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS (0.406 - 0.610)
H8(TO-5) 0.200 PCD 1197
J8 Package 8-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.405 (10.287) MAX 8 7 6 5
0.005 (0.127) MIN
0.023 - 0.045 (0.584 - 1.143) HALF LEAD OPTION
0.025 (0.635) RAD TYP 1 2 3
0.220 - 0.310 (5.588 - 7.874)
4
0.200 (5.080) MAX 0.015 - 0.060 (0.381 - 1.524)
0 - 15
0.045 - 0.068 (1.143 - 1.727) 0.014 - 0.026 (0.360 - 0.660)
0.125 3.175 0.100 0.010 MIN (2.540 0.254)
J8 1197
13
LT1054/LT1054L
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
14
U
Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.255 0.015* (6.477 0.381)
1
2
3
4 0.130 0.005 (3.302 0.127)
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076) N8 1197
0.100 0.010 (2.540 0.254)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
LT1054/LT1054L
PACKAGE DESCRIPTION
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0 - 8 TYP 0.093 - 0.104 (2.362 - 2.642) 0.037 - 0.045 (0.940 - 1.143)
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
S16 (WIDE) 0396
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Dimensions in inches (millimeters) unless otherwise noted.
SW Package 16-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.398 - 0.413* (10.109 - 10.490) 16 15 14 13 12 11 10 9
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
1
2
3
4
5
6
7
8
0.050 (1.270) TYP
0.004 - 0.012 (0.102 - 0.305)
0.014 - 0.019 (0.356 - 0.482) TYP
15
LT1054/LT1054L
TYPICAL APPLICATIONS N
Positive Doubler with Regulation
VIN = 5V 50k 1N5817 VOUT 8V 50mA
+ +
1N5817 0.03F 5.5k
10F
10k 5V
100F
0.1F
LT1054 * TA13
|VOUT| |VOUT| R2 = +1 = + 1 , REFER TO FIGURE 5 1.21V R1 VREF - 40mV LT1054 * TA14 2
)
)) )
THE TYPICAL APPLICATIONS CIRCUITS WERE VERIFIED USING THE STANDARD LT1054. FOR S8 APPLICATIONS ASSISTANCE IN ANY OF THE UNUSUAL APPLICATIONS CIRCUITS PLEASE CONSULT THE FACTORY
RELATED PARTS
PART NUMBER LTC1144 LTC1514/LTC1515 LT1611 LT1614 DESCRIPTION Switched-Capacitor Voltage Converter Step-Up/Step-Down Switched Capacitor DC/DC Converters Micropower Inverting DC/DC Converter Micropower Inverting DC/DC Converter COMMENTS Wide Input Voltage Range, 2V to 18V Regulated 5V Doublers 150mA Output 250mA Output
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1054ld LT/TP 1298 2K REV D * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1987
+
+
2.5k
-
10k
10F
10k LT1006
1N4001
VIN = 3.5V TO 15V VOUT(MAX) -2VIN + (VL + 2VDIODE) VL = LT1054 VOLTAGE LOSS
+
U
Negative Doubler with Regulator
VIN 3.5V TO 15V
+
FB/SHDN
+
V+
2F
FB/SHDN V +
+
2F
OSC CAP LT1054 GND VREF CAP - VOUT
+
10F
OSC CAP + LT1054 GND VREF CAP - VOUT
R1, 20k 100F 1N4001 -VOUT 100F R2 1M 0.002F
+

▲Up To Search▲

Price & Availability of LT1054

	To Download LT1054 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .